So in Electrical Engineering, and I’m sure in some of the other Engineering majors as well, Junior and Senior year classes commonly come with end of the semester design projects. I think this is actually a lot of fun, despite the extra workload, because I get to be creative and work on things that I find interesting. This semester I have design projects in two of my Electrical Engineering classes: EE201 Introduction to Digital Circuits, and EE301 Introduction to Linear Systems.

In this post, I’m going to talk about the project I’m working on for EE201 with Steve, who is another VSA. For those of you who don’t know, Steve and I were both huge Pokemon fans as kids (and still are now)! So when we were assigned to do a design project using a Nexys-3 FPGA (Field Programmable Gate Array), we decided to model a Pokemon battle. Each player gets to choose six Pokemon and then the two players battle until one of the players has had all six of their Pokemon knocked out.

Nexys-3 Field Programmable Gate Array

Another thing you may not know about me and Steve is that we a\are ridiculous overachievers. So this game is actually a lot more work than is intended to fit into this 3-week design project. We started the preliminary work and it’s been pretty fun so far! Fair warning: This blog is about to get a little technical so…just fyi!

First we decided which features from the original battle system we wanted to include, since we have limited time and can’t do everything. Then we wrote the state machine for the design. The state machine shows all the different states that the game can be in and what causes the transition between states. For example, there is one state in which player one chooses their six Pokemon, and the state then transitions to the next state after the sixth Pokemon is chosen. We decided to store the stats of the Pokemon and their attacks in ROMs, and then when the players select a Pokemon, the values in that ROM is saved in a register that can be modified through the rest of the battle.

A messy drawing of our state machine!

Although it’s complicated, it was actually really fun to think through how we could best design it! We think we’ve got a pretty good idea of the outline for how everything will work, but the next step is to actually code it in Verilog. Coding the state machine and the output function logic will be the easy part! The hard part is going to be to get the design to interface properly with the FPGA and other devices. We want to be able to output text to the computer and also have some sort of primitive visual representation on the monitor by using the VGA capability of the FPGA.

Basically, we’re in the beginning stages of the design, but it’s been a ton of fun so far! I’ll probably be blogging soon about my design project in my other class! Also, stay tuned for updates from me and Steve about our progress on the Pokemon battle design!